1. Field of the Invention
The present invention relates generally to the use of resonant tunneling devices in logic circuits, and particularly to the use of resonant tunneling diodes and conventional MOSFETs within logic circuits and adder circuits.
2. Background and Objects of the Present Invention
Modern integrated circuits rely on scaling of numerous electronic devices in order to perform various tasks almost instantaneously. In order to create and scale these electronic devices, a combination of semiconductor materials can be used. A semiconductor is an element with a valence of four, which means that an isolated atom of the material has four electrons in its outer or valence orbit. Electrons in the valence orbit are only weakly attracted by the nucleus of the atom, and thus, can be dislodged from the valence orbit to become free electrons. When a free electron is dislodged from the valence orbit, a vacancy is left in the valence orbit, called a hole. The hole behaves like a positive charge, which will attract and capture any electron in the immediate vicinity.
A semiconductor, e.g., silicon or germanium, can be doped to have an excess of free electrons or an excess of holes. A semiconductor material that has been doped with a pentavalent impurity, which has five valence electrons, is called an n-type semiconductor. In n-type semiconductors, the free electrons outnumber the holes, and therefore, the flow of the free electrons (majority carriers) has a much greater effect on the conductivity of the material than the holes (minority carriers). A semiconductor material doped with a trivalent impurity, which has three valence electrons, is called a p-type semiconductor. In such p-type semiconductor material, the holes are the majority carriers and the free electrons are the minority carriers.
One electronic device containing a combination of both p-type and n-type semiconductor material is a diode. When a diode is forward biased, e.g., a negative dc source terminal is connected to the n-type material and a positive dc source terminal is connected to the p-type material, current flows through the circuit because the free electrons in the n-type material and the holes in the p-type material flow towards the junction between the n-type and p-type material. The free electrons in the n-type material combine with the holes in the p-type material to become valence electrons, which can then move through the holes in the p-type material and enter the external circuit to flow towards the positive source terminal.
When the dc source is turned around, such that the negative source terminal is connected to the p-type material and the positive source terminal is connected to the n-type material, the connection is reverse-biased, and current does not flow. This is due to the fact that the holes and free electrons are now attracted toward the source terminals, and therefore, flow away from the junction between the p-type and n-type material (pn junction), thus creating a wide depletion layer. A depletion layer is an area at the pn junction, which contains pairs of positive and negative ions, created by the flow of holes and electrons away from the pn junction.
However, when a diode is heavily doped, the depletion layer is very narrow, and thus the electric field across the depletion layer is very intense. Therefore, when the diode is reverse biased and the field strength reaches approximately 300,000 Volts/centimeter, the field is intense enough to pull electrons out of their valence orbits, which is known as the Zener effect. By increasing the doping level even further, a tunnel diode is created, which exhibits a phenomenon known as negative resistance, which means that an increase in forward voltage produces a decrease in forward current, at least over part of the forward curve. A resonant tunneling diode (RTD) is functionally similar to a tunneling diode, except that it is based upon the resonance of the electron wave function within a quantum well, which is a layer of sufficiently thin narrow-band gap material surrounded by a wide-band gap material. The well is flanked by thin layers of material (comparable to the electron wavelengths), called tunnel barriers, which are slightly transparent to the electron wave. At resonance, the RTD exhibits a pronounced current peak followed by a region of negative differential resistance (NDR). An RTD is a bi-stable device, which means that it can support two stable states with a transient state connecting them.
Another device which utilizes n-type and p-type semiconductor material is the transistor. As shown in FIG. 1 of the drawings, one type of transistor, known as the enhancement-mode Metal Oxide Semiconductor Field Effect Transistor (MOSFET), is made up of two layers of n-type material, the source 10 and the drain 20, separated by a layer of p-type material 30 (called the substrate) to create an NMOSFET. Alternatively, two layers of p-type material can be separated by a layer of n-type material to create a PMOSFET, which works in the same way as an NMOSFET, except that the voltages and currents are reversed. Both the NMOSFET and the PMOSFET contain an insulated gate 40 overlying the semiconductor body 10, 20 and 30, which includes a metallic layer 45 overlying a thin layer of silicon dioxide 42, or other insulator. When the gate voltage (Vgs) is zero, the current between the source 10 and the drain 20 is negligible. However, when the gate voltage (Vgs) is positive enough, e.g., above a threshold voltage, the gate 40 attracts minority carriers into a surface channel 50, forming a conductive path between the source 10 and the drain 20. As additional attractive charges are placed on the gate 40 side, e.g., the gate voltage (Vgs) is increased, the channel 50 side draws a balancing of minority carriers from the source 10 and the drain 20 and the channel 50 width increases, thereby increasing the current. In addition, by increasing the source-drain voltage (Vdd), the current between the source 10 and the drain 20 increases approximately linearly at low source-drain voltages (Vdd).
Complementary MOS (CMOS) circuits can be built using PMOSFETs and NMOSFETs, such that when one device is on, e.g., current is flowing, the other device is off. The key advantage to using CMOS design is its extremely low power consumption, which makes the design popular in calculators, digital watches and satellites. For example, CMOS circuits can be used in various logic circuits, such as AND, OR, NAND, NOR, and XOR circuits. For example, a CMOS NAND gate can be constructed using two PMOSFET's in parallel, one for each input, with each PMOSFET having an NMOSFET in series with it.
Another type of CMOS logic circuit, illustrated in FIG. 2 of the drawings, is the MOSFET inverter switch, which is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminals (V.sub.G1 and V.sub.G2) of the PMOSFET Q.sub.1 and NMOSFET Q.sub.2 as to the source terminal (V.sub.DD). For example, the NMOSFET Q.sub.2 is turned on and has a very low channel resistance when a high voltage with respect to the source (V.sub.DD) is applied to the gate (V.sub.G2), and the PMOSFET Q.sub.1 is turned on and has a very low channel resistance when a negative voltage with respect to the source (V.sub.DD) is applied to the gate (V.sub.G1). Therefore, when a high voltage is applied to the input, the PMOSFET Q.sub.1 will be turned off and the NMOSFET Q.sub.2 will be turned on, which will cause the output voltage to be low. Alternatively, when a low voltage is applied to the input, the PMOSFET Q.sub.1 will be turned on and the NMOSFET Q.sub.2 will be turned off, which will cause the output voltage to be high.
CMOS logic style gates with multiple inputs require multiple MOSFETs in series, which increases the propagation delay. For example, as shown in FIG. 3 of the drawings, in a multiple input CMOS OR/NOR circuit, by increasing the number of input voltages (V.sub.in1, V.sub.in2, . . . V.sub.ini, V.sub.inj), and thus the number of respective input NMOSFET transistors (n.sub.1, n.sub.2, . . . n.sub.i, n.sub.j) in parallel, the number of PMOSFET transistors (p.sub.1, p.sub.2, . . . p.sub.i, p.sub.j) in series also increases, which increases the propagation delay since the output (V.sub.nor) has to charge or discharge through a series of transistors (p.sub.1, p.sub.2, . . . p.sub.i, p.sub.j) before it can be fed through an inverter, which includes an additional PMOSFET (Pa) and NMOSFET (Na), to generate the OR signal (V.sub.or).
It is, therefore, an object of the invention to decrease the propagation delay in digital logic circuits.
It is a further object of the invention to reduce the number of devices which need to be implemented within a digital logic circuit.